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Ordering number : ENN*6744
CMOS IC
LC86E5632
8-Bit Single Chip Microcontroller with the One-Time Programmable UVEPROM
Preliminary Overview
The LC86E5632 is a CMOS 8-bit single chip microcontroller with one-time UVEPROM for the LC865600 series. This microcontroller has the function and the pin description of the LC865600 series mask ROM version, and 32K-byte EPROM. The program data is rewritable. It is suitable to developing the program.
Features
(1) Option switching by EPROM data The option function of the LC865600 series can be specified by the EPROM data. LC86E5632 can be checked the function of the trial pieces using the mass production board. (2) Internal one-time EPROM capacity : 32768 bytes (3) Internal RAM capacity : 512 bytes
Mask ROM version LC865632 LC865628 LC865624 LC865620 LC865616 LC865612 LC865608 PROM capacity 32512 bytes 28672 bytes 24576 bytes 20480 bytes 16384 bytes 12288 bytes 8192 bytes RAM capacity 512 bytes 512 bytes 512 bytes 384 bytes 384 bytes 384 bytes 384 bytes
Programming service
We offers various services at nominal charges. These include the ROM writing, the ROM reading, the package stamping and the screening. Contact our representative for further information.
Ver.1.02 30399
91400 RM (IM) HK No.6744-1/21
LC86E5632 (4) Operating supply voltage : 4.5V to 6.0V (5) Instruction cycle time : 0.98s to 400s (6) Operating temperature : +10C to +40C (7) The pin compatible with mask ROM version (8) Applicable mask ROM version : LC865632/ LC865628/ LC865624/LC865620/LC865616/ LC865612/ LC865608 (9) Factory shipment : DIC64S, QFC64E
Notice for use
LC86E5632 is provided for the first release and small shipping of the LC865600 series. At using, take notice of the followings. (1) A point of difference LC86E5632 and LC865600 series
Item Port form at reset Operation after reset releasing LC86E5632 Please refer "Port form at reset" on next page. The option is specified until 3ms after going to a `H' level to the reset terminal by dgrees. The program is executed from 00H of the program counter. The program is executed from 00H of the program counter immediately after going to a `H' level to reset terminal. LC865632/28/24/20/16/12/08
Operating supply voltage range (VDD) Operating temperature range (Topg) Total output current [IOAH(1)] [IOAH(2)] Power dissipation [IDDOP(1)] [IDDOP(2)] [IDDOP(3)] [IDDOP(4)]
4.5V to 6.0V +10C to +40C
2.7V to 6.0V -30C to +70C
Refer to `electrical characteristics' on the semiconductor news.
* A kind of the option corresponding of the LC86E5632
A kind of option Input/output form of Input/output ports Pins, Circuits Port 0 (Specified in a bit) Contents of the option 1. Input Output 2. Input Output 1. Input Output 2. Input Output 1. Input Output 2. Input Output : No pull-up MOS Tr. : N-channel open drain : Pull-up MOS Tr. : CMOS : Programmable pull-up MOS Tr. : N-channel open drain : Programmable pull-up MOS Tr. : CMOS : No Programmable pull-up MOS Tr. : N-channel open drain : Programmable pull-up MOS Tr. : CMOS
Port 1,2 (Specified in a bit)
Port 3,4,5 (Specified in a bit)
Pull-up MOS Tr. Of port7
port7 (Specified in a bit)
1. Pull-up MOS Tr. not provided 2. Pull-up MOS Tr. provided * P74 has on pull-up resistor option.
The port operation related the option is different at reset. Refer to the next table.
No.6744-2/21
LC86E5632 *Port form at reset
Pin P0 Contents of the option Input : Not pull-up MOS Tr. Output : N-channel open drain Input : Pull-up MOS Tr. Output : CMOS LC86E5632 (Same as the mask version) Input mode *The pull-up MOS Tr. is not provided during reset or several hundred microseconds after releasing reset. After that, the pull-up MOS Tr. is provided. (Output is OFF) (Same as the mask version) LC865632/28/24/20/16/12/08 Input mode without pull-up MOS Tr. (Output is OFF) Input mode without pull-up MOS Tr. (Output is OFF)
P1, P2
: Programmable pull-up MOS Tr. Output : N-channel open drain : Programmable pull-up MOS Tr. Output : CMOS Input
Input
Input mode without pull-up MOS Tr. (Output is OFF) Input mode without pull-up MOS Tr. (Output is OFF) Input mode without pull-up MOS Tr. (Output is OFF) Input mode without pull-up MOS Tr. (Output is OFF) Input mode without pull-up MOS Tr. Input mode without pull-up MOS Tr.
(Same as the mask version)
P3, P4, P5
Input
: Not Programmable pull-up MOS Tr. Output : N-channel open drain : Programmable pull-up MOS Tr. Output : CMOS Input
(Same as the mask version)
(Same as the mask version)
P7
Pull-up MOS Tr. not provided Pull-up MOS Tr. provided
(Same as the mask version) Input mode *The pull-up MOS Tr. is not provided during reset or several hundred microseconds after releasing reset. After that, the pull-up MOS Tr. is provided.
(2) Option LC86E5632 uses 256 bytes which is addressed on 7F00H to 7FFFH in the program memory as option data area. This area does not affect the execution of program but the program memory capacity of LC865632 is 32512 bytes which is addressed on 0000H to 7EFFH. The option data is created by the option specified program "SU865000.EXE". The created option data is linked to the program area by linkage loader "L865000.EXE".
No.6744-3/21
LC86E5632 (3) ROM space
7FFFH 7F00H 7EFFH 6FFFH 5FFFH 4FFFH 3FFFH 2FFFH 1FFFH
Opt ion data Area 256 bytes Opt ion Data Area Opt ion Data Area Opt ion Data Area Opt ion Data Area Opt ion Data Area Opt ion Data Area
Program area 32K bytes
Program area 28K bytes
Program area 24K bytes
Program area 20K bytes
Program area 16K bytes
Program area 12K bytes
Program area 8K bytes
0000H LC865632 LC865628 LC865624 LC865620 LC865616 LC865612 LC865608
How to use
(1) Specification of option Programming data for EPROM of the LC86E5632 is required. Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P5632. (2) How to program for the EPROM LC86E5632 can be programmed by the EPROM programmer with attachment ; W86EP5032D, W86EP5032Q. * Recommended EPROM programmer
Productor Advantest Andou AVAL Minato electronics EPROM programmer R4945, R4944, R4943 AF-9704 PKW-1100, PKW-3000 MODEL 1890A
* "27512 (Vpp=12.5V) Intel high speed programming" mode available. The address must be set to "0000H to 7FFFH" and a jumper (DASEC) must be set to `OFF' at programming. (3) How to use the data security function "Data security" is the disabled function to read the data of the EPROM. The following is the process in order to execute the data security. 1. Set `ON' the jumper of attachment. 2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data security. It is not a trouble of the EPROM programmer or the LSI. Notes * Data security is not executed when the data of all address have `FF' at the sequence 2 above. * The programming by a sequential operation "BLANKPROGRAMVERIFY" cannot be executed data security at the sequence 2 above. * Set to `OFF' the jumper after executing the data security.
No.6744-4/21
LC86E5632 (4) How to eliminate The programming data can be erased by using the EPROM eraser. (5) Shielding The UVEPROM (ultraviolet erasable programmable ROM) is in it.
Put the seal on the window in use.
Data security
Data security
1 pin mark of LSI
1 pin
Not data security
1 pin
Not data security
W86EP5032D
W86EP5032Q
No.6744-5/21
LC86E5632
Pin Assignment
SANYO:DIC64S
P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/BUZ P17/PWM TEST1 RES XT1/P74 XT2 VSS CF1 CF2 VDD P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P70/INT0 P71/INT1 P72/INT2/T0IN P73/INT3/T0IN P30 P31 P32 P33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P07 P06 P05 P04 P03 P02 P01 P00 P27 P26 P25 P24 P23 P22 P21 P20 VDDVPP VSS P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 P37 P36 P35 P34
TEST1 RES XT1/P74 XT2 VSS CF1 CF2 VDD P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
P17/PWM P16/BUZ P15/SCK1 P14/SI1/SB1 P13/SO1 P12/SCK0 P11/SI0/SB0 P10/SO0 P07 P06 P05 P04 P03 P02 P01 P00
SANYO:QFC64E
P27 P26 P25 P24 P23 P22 P21 P20 VDDVPP VSS P51 P50 P47 P46 P45 P44
P70/INT0 P71/INT1 P72/INT2/T0IN P73/INT3/T0IN P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43
No.6744-6/21
LC86E5632
System Block Diagram
Interrupt Control
IR
PLA A15-A0 D7-D0 TA CE OE DASEC VDDVPP
Standby Control
EPROM Control
CF RC X'tal PC Clock Generator EPROM (32KB)
Base Timer
Bus Interface
ACC
SIO0
Port 1
B Register
SIO1
Port 7
C Register
Timer 0
Port 8 ALU
Timer 1
Port 2
ADC
Port 3
PSW
INT0 to 3 Noise Filtter
Port 4
RAR
Real Time Service
Port 5
RAM
RAM (128 bytes)
Stack Pointer
Port 0
Watch Dog Timer
No.6744-7/21
LC86E5632
LC86E5632 Pin description
Pin name VSS VDD VDDVPP PORT0 P00 to P07 I/O I/O Power pin (-) Power pin (+) Power pin (+) *8-bit input/output port *Input for port 0 interrupt *Input/output in nibble units *Input for HOLD release *8-bit input/output port *Input/output can be specified in a bit unit *Other pin functions P10 SIO0 data output P11 SIO0 data input/bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input/bus input/output P15 SIO1 clock input/output P16 Buzzer output P17 Timer 1 output (PWM0 output) *8-bit input/output port *Input/output can be specified in a bit unit *8-bit input/output port *Input/output can be specified in a bit unit *15V withstand at N-channel open drain output *8-bit input/output port *Input/output can be specified in a bit unit *15V withstand at N-channel open drain output *2-bit input/output port *Input/output can be specified in a bit unit *15V withstand at N-channel open drain output *5-bit input port *Other pin functions P70 : INT0 input/HOLD release/N-channel Tr. output for watchdog timer P71 : INT1 input/HOLD release input P72 : INT2 input/timer 0 event input P73 : INT3 input with noise filter/timer 0 event input P74 : 32.768kHz crystal oscillation terminal XT1 *Interrupt received forms, the vector addresses high low rising falling rising & level falling level INT0 INT1 INT2 INT3 enable enable disable enable enable enable enable disable enable enable enable enable enable disable disable enable enable enable disable disable Function description *Pull-up resistor : Provided/Not provided *Output form : CMOS/N-channel open drain Output form : CMOS/N-channel open drain Option Power for programming PROM mode
PORT1 P10 to P17
I/O
Data line D0 to D7
PORT2 P20 to P27 PORT3 P30 to P37 PORT4 P40 to P47 PORT5 P50 to P51 PORT7
I/O
Output form : CMOS/N-channel open drain Output form : CMOS/N-channel open drain Output form : CMOS/N-channel open drain Output form : CMOS/N-channel open drain *Pull-up resistor : Provided/Not provided (P70,71,72,73) * P74 has no pull-up resistor. Input of PROM control signals DASEC (*1) OE (*2)
CE (*3)
I/O
Address input A7 to A0 Address input A14 to A8 (*5) P47 : TA (*4)
I/O
I/O
P70 P71 to P74
I/O I
vector 03H 0BH 13H 1BH
Continue.
No.6744-8/21
LC86E5632
Pin name PORT8 P80 to 87
RES
I/O I
Function description *8-bit input port *Other function AD input port (AN7 to AN0) Reset pin Test pin Should be left unconnected. *Input pin for 32.768kHz crystal oscillation *Other function : Input port P74 In case of non use, connect to VDD. *Output pin for 32.768kHz crystal oscillation *Other function In case of non use, should be left unconnected. Input pin for the ceramic resonator oscillation Output pin for the ceramic resonator oscillation -
Option -
PROM mode
I O I
-
-
TEST1 XT1/ P74
XT2
O
-
-
CF1 CF2
I O
-
-
All of port options can be specified in bit unit. *1 *2 *3 *4 *5 Memory select input for data security Output enable input Chip enable input TA ! PROM control signal input A14 ! Address input
* Connect like the following figure to reduce noise into a VDD terminal. Short-circuit the VDD terminal to the VDDVPP terminal. Short-circuit the VSS terminal to the VSS terminal.
LSI VDD Power Supply VDDVPP VSS VSS
No.6744-9/21
LC86E5632 1. Absolute Maximum Ratings at VSS=0V and Ta=25C
Ratings typ.
Parameter Supply voltage Input voltage
Symbol
Pins
Conditions VDD=VDDVPP
VDD[V]
min. -0.3 -0.3
max. +7.0 VDD+0.3
unit V
Input/Output voltage
High level output current
Peak output current Total output current Peak output current Total output current
VDDMAX VDD,VDDVPP VI(1) *Ports 71,72,73, 74 *Port 8 * RES VIO(1) *Ports 0,1,2 *Ports 3,4,5 at CMOS output VIO(2) Ports 3,4,5 at N-ch open drain output option IOPH(1) *Ports 0,1,2,3,4,5
-0.3
VDD+0.3
-0.3 *CMOS output *At each pins The total of all pins The total of all pins At each pins At each pins The total of all pins The total of all pins The total of all pins Ta=+10 to+40C Ta=+10 to+40C 10 -65 -4
15 mA
IOAH(1) IOAH(2) IOPL(1) IOPL(2) IOAL(1) IOAL(2) IOAL(3) Pdmax(1) Pdmax(2) Topr Tstg
Ports 0,1,2 Ports 3,4,5 Ports 0,1,2,3,4,5 Port 70 Ports 0,1,70 Port 2 Ports 3,4,5 DIP64S QFP64E
-25 -20 20 15 40 40 80 720 420 40 150
Low level output current
Maximum power dissipation Operating Temperature range Storage Temperature range
mW C
No.6744-10/21
LC86E5632 2. Recommended Operating Range at Ta=+10C to +40C, VSS=0V
Ratings typ.
Parameter Operating Supply voltage Hold voltage
Symbol VDD(1) VHD VDD VDD
Pins
Conditions 0.98s tCYC tCYC 400s RAMs and the registers hold voltage at HOLD mode. Output disable Output disable Output N-channel Tr. OFF
VDD[V]
min. 4.5 2.0
max. 6.0 6.0
unit V
Input high voltage
VIH(1) VIH(2) VIH(3)
Port 0
(Schmitt)
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
VIH(4) VIH(5) VIH(6) VIH(7) Input low voltage VIL(1) VIL(2) VIL(3)
VIL(4) VIL(5) Operation tCYC cycle time Oscillation FmCF(1) frequency range (Note 1) FmCF(2)
*Ports 1,2 *Ports 72,73 (Schmitt) *Port 70 (Port input/interrupt) *Port 71 (Schmitt) * RES Port 70 (Watchdog timer) *Port 74 *Port 8 Ports 3,4,5 of CMOS output (Schmitt) Ports 3,4,5 of open drain output (Schmitt) Port 0 (Schmitt) *Ports 1,2,3,4,5 *Ports 72,73 (Schmitt) *Port 70 (Port input/interrupt) *Port 71 (Schmitt) * RES Port 70 (Watchdog timer) *Port 74 *Port 8
0. 4VDD +0.9 0.75VDD 0.75VDD
VDD VDD VDD
Output N-channel Tr. OFF Output N-channel Tr. OFF Output disable Output disable Output disable Output disable N-channel Tr.OFF
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
0.9VDD 0.75VDD 0.75VDD 0.75VDD VSS VSS VSS
VDD VDD VDD 13.5 0.2VDD 0.25VDD 0.25VDD
N-channel Tr.OFF N-channel Tr.OFF
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
VSS VSS 0.98 6
0.8VDD -1.0 0.25VDD 400 s MHz
CF1, CF2
CF1, CF2
FmRC FsXtal
XT1, XT2
*6MHz (ceramic resonator oscillation) *Refer to figure 1 *1.5MHz (ceramic resonator oscillation) *Refer to figure 1 RC oscillation *32.768kHz (crystal oscillation) *Refer to figure 2
4.5 to 6.0
4.5 to 6.0
1.5
4.5 to 6.0 4.5 to 6.0
0.3
0.8 32.768
3.0 kHz
Continue.
No.6744-11/21
LC86E5632
Ratings typ.
Parameter Oscillation stabilizing time period (Note 1)
Symbol tmsCF(1)
Pins CF1, CF2
Conditions *6MHz (ceramic resonator oscillation) *Refer to figure 3 *1.5MHz (ceramic resonator oscillation) *Refer to figure 3 *32.768kHz (crystal oscillation) *Refer to figure 3
VDD[V] 4.5 to 6.0
min.
max.
unit ms
tmsCF(2)
CF1, CF2
4.5 to 6.0
tssXtal
XT1, XT2
4.5 to 6.0
s
(Note 1) The oscillation constant is shown on table 1 and table 2.
No.6744-12/21
LC86E5632 3. Electrical Characteristics at Ta=+10C to +40C, VSS=0V
Parameter Input high current Symbol IIH(1) Pins Ports 3,4,5 at open drain output Conditions *Output disable *VIN=13.5V (including off-leakage current of the output Tr.) *Output disable *Pull-up MOS Tr. OFF. *VIN=VDD (including off-leakage current of the output Tr.) VIN=VDD Ratings typ. unit A
VDD[V] 4.5 to 6.0
min.
max. 5
IIH(2)
*Port 0 without pull-up MOS Tr. *Ports 1,2,3,4,5
4.5 to 6.0
1
IIH(3)
Input low current
IIH(4) IIL(1)
*Ports 70,71,72,73 without pull-up MOS Tr. *Port 8 RES *Ports 1,2,3,4,5 *Port 0 without pull-up MOS Tr.
4.5 to 6.0
1
IIL(2)
Output high voltage Output low voltage
IIL(3) VOH(1) VOH(2) VOL(1) VOL(2) VOL(3) VOL(4) Rpu VHIS
*Ports 70,71,72,73 without pull-up MOS Tr. *Port 8 RES Ports 0,1,2,3,4,5 at CMOS output Ports 0,1,2,3,4,5 Port 70 *Ports 0,1,2,3,4,5 *Ports 70,71,72,73 *Ports 0,1,2,3,4,5 *Ports 70,71,72,73 * RES All pins
VIN=VDD *Output disable *Pull-up MOS Tr. OFF. *VIN=VSS (including off-leakage current of the output Tr.) VIN=VSS
4.5 to 6.0 4.5 to 6.0
1 -1
4.5 to 6.0
-1
VIN=VSS IOH=-1.0mA IOH=-0.1mA IOL=10mA IOL=1.6mA IOL=1mA IOL=0.5mA VOH=0.9VDD Output disable
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
-1 VDD-1 VDD-0.5 1.5 0.4 0.4 0.4 15 40
0.1VDD
V
Pull-up MOS Tr. resistor Hysteresis voltage
70
k V
Pin capacitance CP
*f=1MHz *VIN=VSS for all unmeasured terminals. *Ta=25C
4.5 to 6.0
10
pF
No.6744-13/21
LC86E5632 4. Serial Input/Output Characteristics at Ta=+10C to +40C, VSS=0V
Ratings typ.
Parameter Cycle Low Level pulse width High Level pulse width Cycle Low Level pulse width High Level pulse width Input clock
Symbol tCKCY(1) tCKL(1) tCKH(1) tCKCY(2) tCKL(2) tCKH(2) tICK tCKI
Pins SCK0, SCK1
Conditions Refer to figure 5
VDD[V] 4.5 to 6.0
min. 2 1 1
max.
unit tCYC
Serial clock
Output clock
SCK0, SCK1
*Use pull-up resistor (1k) in the open drain output. *Refer to figure 5 *Data set-up to SCK0,1 *Data hold from SCK0,1 *Refer to figure 5 *Use pull-up resistor (1k) in the open drain output. *Data hold from SCK0,1 *Refer to figure 5
4.5 to 6.0
2 1/2tCKCY 1/2tCKCY
Serial input
Data set-up time Data hold time
*SI0,SI1 *SB0,SB1
4.5 to 6.0
0.1 0.1
s
Output delay time (External clock using for serial transfer clock) Output delay time (Internal clock using for serial transfer clock)
tCKO(1)
*SO0,SO1 *SB0,SB1
4.5 to 6.0
7/12 tCYC
+0.2
Serial output
tCKO(2)
1/3 tCYC
+0.2
No.6744-14/21
LC86E5632 5. Pulse Input Conditions at Ta=+10C to +40C, VSS=0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIL(4) Pins *INT0, INT1 *INT2/T0IN *INT3 INT3 (The noise rejection clock selected to 1/1.) INT3 (The noise rejection clock selected to 1/16.) RES Conditions *Interrupt acceptable *Timer0-countable *Interrupt acceptable *Timer0-countable *Interrupt acceptable *Timer0-countable Reset acceptable Ratings typ. max. unit tCYC
VDD[V] 4.5 to 6.0
min. 1
4.5 to 6.0
2
4.5 to 6.0
32
4.5 to 6.0
200
s
6. AD Converter Characteristics at Ta=+10C to + 40C, VSS=0V
Parameter Resolution Absolute precision (Note 2) Conversion time Symbol N ET tCAD AD conversion time = 16 x tCYC (ADCR2=0) (Note 3) AD conversion time = 32 x tCYC (ADCR2=1) (Note 3) AN0 to AN7 VAIN=VDD VAIN=VSS Pins Conditions Ratings typ. 8 1.5 15.68 (tCYC= 0.98s) 31.36 (tCYC= 0.98s) VSS 65.28 (tCYC= 4.08s) 130.56 (tCYC= 4.08s) VDD 1 -1 unit bit LSB s
VDD[V] 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
min.
max.
Analog input voltage range Analog port input current
VAIN IAINH IAINL
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
V A
(Note 2) Absolute precision excepts the quantizing error (1/2 LSB). (Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital conversion value to the register.
No.6744-15/21
LC86E5632 7. Current Dissipation Characteristics at Ta=+10C to +40C, VSS=0V
Parameter Current dissipation during basic operation (Note 4) Symbol IDDOP(1) Pins VDD Conditions *FmCF=6MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : CF oscillation *Internal RC oscillation stops *FmCF=1.5MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : CF oscillation *Internal RC oscillation stops *FmCF=0Hz (The oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock : RC oscillation *FmCF=0Hz (The oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock : 32.768kHz *Internal RC oscillation stops Ratings typ. 13 unit mA
VDD[V] 4.5 to 6.0
min.
max. 26
IDDOP(2)
4.5 to 6.0
7
14
IDDOP(3)
4.5 to 6.0
4
10
IDDOP(4)
4.5 to 6.0
4
8
Continue.
No.6744-16/21
LC86E5632
Ratings typ. 5
Parameter Current dissipation in HALT mode (Note 4)
Symbol IDDHALT(1)
Pins
Conditions *HALT mode *FmCF=6MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : CF oscillation *Internal RC oscillation stops *HALT mode *FmCF=1.5MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : CF oscillation *Internal RC oscillation stops *HALT mode FmCF=0Hz (The oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock : RC oscillation *HALT mode FmCF=0Hz (The oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock : 32.768kHz *Internal RC oscillation stops HOLD mode
VDD[V] 4.5 to 6.0
min.
max. 10
unit mA
IDDHALT(2)
4.5 to 6.0
2.2
4.6
IDDHALT(3)
4.5 to 6.0
550
1000
A
IDDHALT(4)
4.5 to 6.0
25
100
Current dissipation in HOLD mode (Note 4)
IDDHOLD(1) IDDHOLD(2)
VDD
4.5 to 6.0 2.5 to 4.5
0.05 0.02
30 20
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
No.6744-17/21
LC86E5632
Table 1. Ceramic resonator oscillation recommended constant (main clock)
Oscillation type 12MHz ceramic resonator oscillation 3MHz ceramic resonator oscillation Maker Murata Oscillator CSA12.0MTZ CSA12.0MTZ CST12.0MTW CSA3.00MG040 CST3.00MGW040 C1 C2 Rf OPEN OPEN OPEN OPEN OPEN Rd 560 0 560 1.5 1.5 33pF 33pF 39pF 30pF on chip 100pF 100pF on chip
Murata
* Both C1 and C2 must use K rank (10%) and SL characteristics. Table 2. Crystal oscillation recommended constant (sub clock)
Oscillation type 32.768kHz crystal oscillation Maker Kyocera Seiko Epson Oscillator KF-38G-13P0200 MC-306,C-002RX,32.768kHz C3 18pF 4pF C4 18pF 4pF
* Both C3 and C4 must use J rank (5%) and CH characteristics. (It is about the application which is not in need of high precision. Use K rank (10%) and SL characteristics.) (Notes) *Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length.
CF1 Rf
CF2
XT1
XT2
Rd X'tal C1 CF C2 C3 C4
Figure 1
Main-clock circuit Ceramic oscillation circuit
Figure 2
Sub-clock circuit Crystal oscillation
No.6744-18/21
LC86E5632
VDD Power supply Reset time VDD limit OV RES
Interrnal RC resonator oscillation CF1, CF2
tmsCF
tssXtal XT1, XT2
Operation mode
Unfixed
Reset
Instruction execution mode
< Reset time and oscillation stabilizing time. >
HOLD release signal Interrnal RC resonator oscillation CF1, CF2
Valid
tmsCF
tssXtal XT1, XT2
Operation mode
HOLD
Instruction execution mode
< HOLD release signal and oscillation stabilizing time. >
Figure 3
Oscillation stable time
No.6744-19/21
LC86E5632
VDD
RRES
RES CRES
(Note) Fix the value of CRES, RRES that is sure to reset until 200s, after Power supply has been over inferior limit of supply voltage.
Figure 4
Reset circuit
0.5VDD
tCKCY tCKL SCK0 SCK1 tICK SI0 SI1 tCKO SO0, SO1 SB0, SB1

VDD tCKH 1K
tCKI
50pF

Figure 5
Serial input / output test condition
tPIL
tPIH
Figure 6
Pulse input timing condition
No.6744-20/21
LC86E5632
PS No.6744-21/21

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